Mentor Graphics Tessent 2021.2 for linux

Tessent DefectSim works with Mentor’s Eldo® and Questa® ADMS™ circuit simulators to measure the effects of opens, shorts, extreme variations, and user-defined defects modeled within a layout-extracted or schematic netlist. A number of techniques are used to reduce total simulation time by many orders of magnitude, compared to sequential simulation of every defect in a flat layout-extracted netlist, without reducing simulation accuracy or limiting the type of test. Among the techniques is a new statistical method called likelihood-weighted random sampling that minimizes the number of defects to simulate and more accurately indicates outgoing chip quality.

Tessent DefectSim can also measure a circuit’s tolerance to defects. Defect tolerance is a measure of a circuit’s ability, in the presence of defects, to either continue to operate within acceptable operational limits or to transition into a safe state. This metric is very important in automotive applications as it directly relates to long term reliability.